Tensilica Enhances Reference Flow with Cadence Encounter RTL Compiler

Tensilica incorporated Cadence Encounter RTL Compiler with global synthesis in its CAD flow which supports both Diamond and Xtensa cores. Encounter RTL Compiler with global synthesis enables Tensilica customers to achieve smaller, faster and lower-power implementations for microprocessor designs using Tensilica IP.

With the RTL Compiler multi-objective optimization, customers can achieve significant advantages in area, speed and performance. In tests, Tensilica achieved a 10 percent increase in speed and a reduction of cell area of 5 percent. The RTL Compiler global synthesis solution improves performance, reduces die sizes, lowers power consumption, and speeds up design closure through place and route.

For more information: http://www.tensilica.com/news_events/pr_2007_06_19_cadence.htm

Aftek Becomes Tensilica Configurable Processor Design Center

Aftek Limited is now an authorized Design Center partner for customers using Xtensa configurable processors, Diamond Standard Processors, and the Xtensa HiFi 2 Audio Engine in their SOC (system on chip) designs.

Aftek has considerable expertise in IP (intellectual property) integration as well as the development of system and chip specifications, hardware-software partitioning, development of reference models, and analysis of performance trade-offs. They have successful tape outs in 90nm and 130nm process technologies. They have a rich knowledge base in domains such as networking, multimedia processing, DSP (digital signal processing), connectivity, and wireless low power SOC design.

For more information, see http://www.tensilica.com/news_events/pr_2007_06_19.htm

DesignArt Networks Picks Xtensa LX2 for WiMax

“By using Tensilica’s Xtensa LX2 configurable processors in our SOC, we took our platform to a higher level of flexibility, and we are able to bring a highly configurable silicon platform to our customers. The benefits are clear – better ability of tracking customer requirements and standards evolution, as well as an in-field software upgradeable network infrastructure,” stated Oz Barak, CEO, DesignArt Networks.

“In the PHY, the powerful Xtensa LX2 DSP core enables the implementation of various MIMO receiver configurations. In the MAC layer, the Xtensa LX2 processors are the engine of the embedded high packet rate network processor, forming a highly-configurable design to track the future 802.16e standard evolution, as well as the emerging 802.16j standard. The robustness and sophistication of the Xtensa toolset allowed us to have packets traversing an RTL simulation on day 2 of the development effort. Today, these multi-core subsystems are up and running on the FPGA boards in our integration labs, with several months of testing already completed.”

For more information, see http://www.tensilica.com/news_events/pr_2007_06_14.htm

Why High MHz Does Not Mean High Performance

Do you think that high MHz = high performance? The PC industry tried to teach us that, but it simply isn't true. There are a lot of other factors, and often you can get higher performance out of an optimized lower MHz processor. See the article on SOCcentral.com at:
http://www.soccentral.com/results.asp?CatID=488&EntryID=22911

Achieving Very High Performance in the Networking Data Plane

Sign up now for Tensilica's next Techonline Seminar: Achieving Very High Performance in the Networking Data Plane. We'll be giving this seminar on Wednesdy, June 27 at 10 am Pacific time (1 pm EST). Sign up at
http://seminar2.techonline.com/registration/distrib.cgi?s=1096&d=1062

Tensilica Announces Industry’s First MP3 Decoder Under 6 MHz

Tensilica has optimized the MP3 decoder for its Xtensa HiFi 2 Audio Engine and Diamond Standard 330HiFi processor core. This MP3 decoder now runs at the lowest power and is the most efficient in the industry, requiring just 5.7 MHz when running at 128Kbps, 44.1 KHz and dissipating 0.45 mW in TSMC’s 65nm LP process (including memories). This makes Tensilica’s Xtensa HiFi 2 Audio Engine ideal for adding MP3 playback to cellular phones, where current carrier requirements are for 100 hours of playback time on a battery charge, and increasing to 200 hours in the near future.

This 5.7 MHz requirement includes the entire MP3 decode functionality, including MPEG container parsing and variable length decoding (VLD, also known as Huffman decoding). Some competing offerings are merely accelerator blocks that exclude portions of the complex control code in MP3 such as VLD, and thus rely on a processor to perform VLD decoding. Tensilica’s 5.7 MHz figure is all inclusive.

For more information, see http://www.tensilica.com/news_events/pr_2007_05_16.htm

Two Korean Universities License Xtensa

The CoSoC (Center of System on Chip design technology) of Seoul National University is using Xtensa processors in the classroom and has announced their third annual SOC design contest, which will, for the first timie, accept designs that use Xtensa processors.

The KAIST (Korea Advanced Institute of Science and Technology) has licensed Xtensa to develop multimedia SOC designs.

Our agreement with these two universities underscores our dedication to working with universities around the world to train next-generation design engineers. We now have over 80 universities worldwide that use Xtensa processors in their research and/or classrooms.