EDN Magazine (www.ednmag.com) named the Tensilica Diamond Standard Processor family to its list of Hot 100 Products of 2006.
According to EDN, “Built by and for electronics engineers, this list distills the most innovative and significant products of the year, including process technologies, power sources, processor cores, communication controllers, test instruments, embedded boards, EDA tools, and more.
“Our editors mercilessly cull the herd of new-product announcements they see during the year, resulting in this distillation of the most innovative and significant offerings,” EDN added.
EDN’s Top 100 list can be viewed at http://www.edn.com/article/CA6399100.html.
Tuesday, December 19, 2006
Wirpo is Tensilica's Newest Design Center Partner
Wipro Technologies, the global IT Services arm of Wipro Limited (NYSE:WIT), is Tensilica’s newest processor core design center partner. As a Tensilica design center and Tensilica Xtensions Network partner, Wipro will combine its extensive intellectual property (IP) portfolio, systems knowledge, architecture modeling and verification expertise with system-on-chip (SOC) design services for customers using Tensilica’s Xtensa configurable processors or Diamond Standard processor cores.
Madhu Parthasarathy, general manager, DSP & Multimedia Applications, Wipro Technologies, said, “Our advanced algorithm group has been actively evaluating processors to address the low-cost, enhanced computing requirements of applications in the biometric space, such as fingerprint recognition/matching. The Tensilica Diamond processor series meet the requirements and also offers the added advantage of a logically scalable path to extend our algorithms to a wider range of applications that our HW-SW architecture group and the HW acceleration service lines view as essential to cater to the complex SOC requirements in the future.”
Madhu Parthasarathy, general manager, DSP & Multimedia Applications, Wipro Technologies, said, “Our advanced algorithm group has been actively evaluating processors to address the low-cost, enhanced computing requirements of applications in the biometric space, such as fingerprint recognition/matching. The Tensilica Diamond processor series meet the requirements and also offers the added advantage of a logically scalable path to extend our algorithms to a wider range of applications that our HW-SW architecture group and the HW acceleration service lines view as essential to cater to the complex SOC requirements in the future.”
Friday, December 15, 2006
Virage Logic 's Core-Optimized IP Kits
Tensilica Inc. and Virage Logic introduced sixteen specially designed Core-Optimized IP Kits for Tensilica’s Diamond Standard processor family members for manufacture on TSMC’s 130-nanometer (nm) and 90nm G processes. The new Core-Optimized IP Kits consist of Virage Logic’s Area, Speed and Power (ASAP) ASAP Memory™ and ASAP Logic™ IP, and are optimized for each of the Diamond cores to allow designers to target area, performance or power. For more information, see http://www.tensilica.com/news_events/pr_2006_12_11.htm
Tensilica Introduces Four Video Processor Engines Including Main Profile H.264 Support
Tensilica introduced four new Diamond Standard VDO (ViDeO) processor engines customized for multi-standard, multi-resolution video. Targeted at mobile handsets and personal media players (PMPs), these video subsystems are fully programmable to support all popular VGA and standard definition (SD, also known as D1) video codecs with resolutions up to 720x480 (NTSC) and 720x576 (PAL) including H.264 Main Profile, VC-1 Main Profile, MPEG-4 Advanced Simple Profile (ASP), and MPEG-2 Main Profile, each of which is available from Tensilica. Lower resolutions such as QCIF, QVGA, CIF and VGA are also supported.
The Diamond Standard VDO engines host all the key video processing functions in software on the cores – including the network abstraction layer, picture layer, slice layer, bit-stream parsing and entropy decoding and encoding. This includes the computationally demanding CABAC (Context Adaptive Binary Arithmetic Coding) decoding in the H.264 Main profile decoder that most other solutions omit, implement in a separate and complex non-programmable hardware block or necessitate more than 700 MHz of general CPU workload which significantly increases power consumption. By implementing CABAC in instruction set extensions, Tensilica was able to create a low MHz and power efficient version of CABAC in less than half the area of a typical CABAC hardware block.
The Diamond VDO family offers both Baseline and Main profile solutions – Main profile offers superior data compression and video quality and is the preferred coding scheme at resolutions of D1 and higher for advanced handset and PMP applications. Most other video solutions for SOC design only implement Baseline profile video.
The Diamond Standard VDO engines host all the key video processing functions in software on the cores – including the network abstraction layer, picture layer, slice layer, bit-stream parsing and entropy decoding and encoding. This includes the computationally demanding CABAC (Context Adaptive Binary Arithmetic Coding) decoding in the H.264 Main profile decoder that most other solutions omit, implement in a separate and complex non-programmable hardware block or necessitate more than 700 MHz of general CPU workload which significantly increases power consumption. By implementing CABAC in instruction set extensions, Tensilica was able to create a low MHz and power efficient version of CABAC in less than half the area of a typical CABAC hardware block.
The Diamond VDO family offers both Baseline and Main profile solutions – Main profile offers superior data compression and video quality and is the preferred coding scheme at resolutions of D1 and higher for advanced handset and PMP applications. Most other video solutions for SOC design only implement Baseline profile video.
Next Generation Xtensa Configurable Processors
On December 4, Tensilcia introduced its next-generation Xtensa configurable processors, the Xtensa LX2 and Xtensa 7 cores. I was busy traveling around the world doing the press introductions, so I got behind on my blogging. Here's some basic information. The web site is updated to reflect the new products.
Both processors feature several architectural enhancements, and are the first configurable licensable core families available with built-in, on-the-fly Error Correcting Code (ECC), which is extremely important in storage, networking, automotive and transaction processing applications where data integrity and error resiliency are of paramount concern. Tensilica’s new generation of processors reinforce Tensilica’s processor technology leadership by remaining the lowest power, highest performance licensable cores on the market. Both processors are available and shipping now.
See http://www.tensilica.com/news_events/pr_2006_12_04LX2.htm for highlights of what's new in these two processors.
Both processors feature several architectural enhancements, and are the first configurable licensable core families available with built-in, on-the-fly Error Correcting Code (ECC), which is extremely important in storage, networking, automotive and transaction processing applications where data integrity and error resiliency are of paramount concern. Tensilica’s new generation of processors reinforce Tensilica’s processor technology leadership by remaining the lowest power, highest performance licensable cores on the market. Both processors are available and shipping now.
See http://www.tensilica.com/news_events/pr_2006_12_04LX2.htm for highlights of what's new in these two processors.
Friday, December 01, 2006
Lauterbach’s TRACE32® PowerView Debugger Supports
Lauterbach now supports Tensilica’s Diamond Standard and Xtensa configurable processors with its TRACE32 PowerView microprocessor debugger. Lauterbach’s debugger speeds software development on Tensilica’s processor cores.
“Over the past year, we’ve seen increasing demand for our products on both families of Tensilica processors – the Diamond Standard series and the Xtensa configurable processors – as more designers are using these products in their SoC designs,” stated Norbert Weiss, International sales manager from Lauterbach. “Tensilica’s processors are particularly popular in multicore designs, which we service very well with our TRACE32-ICD.”
The PowerDebug (in-circuit debugger) is a high-performance JTAG debugger. The PowerDebug’s hardware consists of a universal debug module that can be connected to any PC or workstation via a USB 2.x or Ethernet interface. The PowerView software supports multicore debugging. Graphical variable displays and dedicated commands to handle large arrays support the development of DSP-specific code. The combination of the debugger and the PowerProbe logic analyzer enables real-time measurements. The PowerView debugger software provides a unified, graphical environment for debugging SoCs with one or more Tensilica processors, or a combination of Tensilica processors plus cores from other vendors in a heterogeneous debug environment.
“Over the past year, we’ve seen increasing demand for our products on both families of Tensilica processors – the Diamond Standard series and the Xtensa configurable processors – as more designers are using these products in their SoC designs,” stated Norbert Weiss, International sales manager from Lauterbach. “Tensilica’s processors are particularly popular in multicore designs, which we service very well with our TRACE32-ICD.”
The PowerDebug (in-circuit debugger) is a high-performance JTAG debugger. The PowerDebug’s hardware consists of a universal debug module that can be connected to any PC or workstation via a USB 2.x or Ethernet interface. The PowerView software supports multicore debugging. Graphical variable displays and dedicated commands to handle large arrays support the development of DSP-specific code. The combination of the debugger and the PowerProbe logic analyzer enables real-time measurements. The PowerView debugger software provides a unified, graphical environment for debugging SoCs with one or more Tensilica processors, or a combination of Tensilica processors plus cores from other vendors in a heterogeneous debug environment.
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