Aquantia Licenses Diamond Standard 108Mini for Next-Generation 10GE Over Copper IC

Aquantia Corp. of Milpitas, Calif., has licensed the Diamond Standard 108Mini processor core for their 10 Gigabit Ethernet physical layer transceiver chip design. Aquantia is developing chips which will enable the upcoming 10GBASE-T standard for operation over familiar UTP (Unshielded Twisted Pair) cabling.

"We liked Tensilica’s Diamond 108Mini because it gave us the performance we needed in a small form factor,” stated Ramin Shirani, vice president of engineering, Aquantia. “With its small footprint and minimal power requirements, the Diamond 108Mini is well suited for general control applications."

For more information, see http://www.tensilica.com/news_events/pr_2006_04_19.htm

Lucid Licenses Diamond 212GP Controller Core

Lucid Information Technology, Ltd., of Kfar Netter, Israel, has licensed Tensilica's Diamond Standard 212GP general-purpose processor core for a new scalable multi-GPU chip design project. The Diamond 212GP is a flexible mid-range RISC controller that includes instruction and data caches, a 16-bit multiply-accumulator, DSP functions and zero-overhead loop support. The Diamond 212GP also includes a single-cycle latency local interface bus. This processor core provides 40 percent better performance and 30 percent lower power than an ARM946E-S processor.

"We particularly liked the in-bound DMA capability of the Diamond Standard series,” stated Moshe Steiner, CEO, Lucid. “With this feature we are able to realize significantly higher computational and data throughput when compared to alternative architectures."

For more information, see http://www.tensilica.com/news_events/pr_2006_04_18.htm

See Diamond SW Tools Demo

Want a peek at the great software tools for our Diamond Standard series? Then check out Demos on Demand at www.demosondemand.com/dod/proddemos/vendors/pd_tensilica.aspx

Free Diamond Core Software Development and Modeling Tools

Tensilica is offering free evaluation versions of the Diamond Standard Software Toolkit, the advanced software development and modeling environment for the Diamond Standard processor core family, which was announced on February 20, 2006. The Toolkit is available for immediate download from Tensilica’s web site at www.tensilica.com.

Software and firmware engineers will want to explore the Diamond processor software development tools to learn how easy it is to port application code to the Diamond core processor family, and to experience the code performance and code size advantages of the Tensilica Xtensa instruction set architecture. Powerful visualization tools enable software developers to graphically view and compare profiling results.

Hardware design teams will want to take advantage of this free evaluation to experiment with the clock-cycle accurate, pipeline-modeling instruction set simulator and the associated performance modeling visualization views within the graphical user interface that show pipeline activity, cache utilization rates, and cycles spent on bus cycle activity.

Tensilica and CSIP of Ministry of Information Industry (MII) of PRC Establish First Joint IP Core Lab

February 23, 2006 - Tensilica, Inc. and CSIP of Ministry of Information Industry (MII) of PRC today announced the establishment of a joint IP core lab during a signing ceremony attended by Ding Wenwu, director of the Product Department of MII, Dr. Qui Shangin, head of CSIP, and Chris Rowen, president and CEO of Tensilica.

“It is our great honor to be the first company to set up an IP core lab with CSIP,” stated Chris Rowen, Tensilica president and CEO. “We will strive to provide world leading processor technology for Chinese clients through this lab so as to accelerate China’s SOC design and create more ICs with independent IP.”

For more information, visit http://www.tensilica.com/news_events/pr_2006_02_23.htm

Tensilica Introduces Diamond Standard processors

Tensilica introduced the Diamond Standard family of processor cores, a set of six off-the-shelf synthesizable cores that range from area-efficient, low-power controllers to high-performance DSPs, all of which lead the industry in their respective categories both in lowest power and highest performance. The Diamond Standard processors are supported by an optimized set of Diamond Standard software tools and a wide range of industry infrastructure partners. They are available directly from Tensilica and through a growing list of ASIC and foundry partners.

This announcement provides Tensilica with the broadest range of off-the-shelf processors in the industry, with the six Diamond Standard cores plus an almost infinite number of processor configuration possibilities for those customers requiring optimized, application-specific processors with Tensilica’s award-winning Xtensa configurable processor family.

For a full list of all Diamond press releases, see http://www.tensilica.com/news_events/press_releases_2006.htm.

Tensilica Establishes India Subsidiary for R&D

Tensilica has set up an Indian subsidiary to conduct fundamental, innovative research and development work for its industry leading configurable processor technology and to be closer to key customers in India. Engineers are already working on critical technology for Tensilica’s Xtensa configurable processor product line at this R&D center, Tensilica Technologies India, located in Pune. For more information, read: http://www.tensilica.com/news_events/pr_2006_02_09.htm

u-Nav Microelectronics Picks Xtensa for GPS Designs

u-Nav Microelectronics, a worldwide leader in ultra-low power Global Positioning Systems (GPS) semiconductors, has picked the Xtensa configurable processors for its next-generation GPS designs, which will be targeted for portable applications such as mobile wireless handsets and consumer devices.

“We selected the Tensilica Xtensa processor because they offered us the most flexibility and achieved the lowest power for a programmable solution,” stated Greg Winner, COO of u-Nav Microelectronics. “With the ability to customize Xtensa through Tensilica’s automated processor generation technology, and the inclusion of u-Nav’s custom instructions, we created a unique way to significantly lower the total power consumption of our complete GPS system-on-chip design.”

For more, see http://www.tensilica.com/news_events/pr_2006_02_06.htm.

MediaWorks and Olympus renew licenses

Both MediaWorks and Olympus renewed their licenses for Tensilica's Xtensa processors.

MediaWorks employs Xtensa processors in their recently announced groundbreaking MediaFlex™ platform architecture and MW301 Media Processor. See http://www.tensilica.com/news_events/pr_2006_01_25.htm
for more information.

Olympus is making its Tensilica license, which now has been expanded to include Xtensa LX, available to its design groups in its Corporate R&D Center in both Japan and the United States. See
http://www.tensilica.com/news_events/pr_2006_01_16.htm
for more information.

E L & Associates Becomes Tensilica Authorized Design Center

E L & Associates, of Pleasanton, Calif., is now an authorized Tensilica design center. E L & Associates already supports several Tensilica customers with their system-on-chip (SOC) design programs, and is a leader in the design (RTL to GDS2), design-for-test (DFT), and design-for-manufacturing (DFM) integrated solutions for complex SOC architectures. For more information, see http://www.tensilica.com/partners/soc_el.htm