Great White Paper from Tensilica

SOC designs are major projects. They can produce high-volume, immensely profitable chips but not without risk, as is true for any big project. Most SOC design projects do not complete on time or on budget. Too many are not completed at all. Although there is some risk involved, the rewards for success are great. These 10 tips will help your team find the path to a successful SOC design.

Get a New Computer for School with Tensilica Inside

All you need to do is get a computer with an AMD Radeon Graphics chip or card inside. Like the new Apple iMacs, or many PCs and notebooks.

Read What BDTI Says about Tensilica's ConnX BBE64 for LTE Advanced

Cellular networks delivering 1Gbps of raw data throughput are on the horizon, and Tensilica is designing a DSP to meet the baseband-processing requirements of such networks: the ConnX Baseband Engine 64 (BBE64). The BBE64 achieves its performance by employing wide execution units that support up to 128x 18-bit operations in parallel, wide 640-bit registers, and massive I/O. The company targets a performance increase of 5-15 times for the BBE64 compared with the currently availablwe BBE16 for LTE.
Read more.

Design Art Networks Announces Tensilica-based Small Cell LTE Reference Designs

Our partner, Design Art Networks (DAN), announced yesterday the availability of several complete compact base station reference designs for compact, low-cost, carrier-grade LTE small cell products.
Ready for immediate productization, DesignArt Networks has tested and released a fully integrated and standards compliant 3GPP LTE PHY software solution, for LTE and LTE Advanced small cell deployments. Combined with the available Unified Mobile Backhaul software pack, DAN3000 base station reference designs represent a fully integrated single-SoC LTE Advanced small cell base station with unified self-backhaul and relay. Read more about this.

Happy Anniversary to Me

It's been 9 years now since I joined Tensilica. Wow, a lot has happened during that time. We went from Xtensa 4 to Xtensa 9, added HiFi Audio DSPs and the ConnX family of baseband DSPs. Started going to the CES and Mobile World Congress trade shows. I was even able to convince the company to install Salesforce and led that project.

Now, as I see the fruits of all this work, things are really looking good around here. We just celebrated shipping our billionth IP core, and we're on target to get to 2 billion cores by the end of 2012. We're hiring like crazy (check out our careers page). Business is good, and I'm glad I stayed. Looking forward to several more good years ahead.

White Paper: Cut DSP Development Time – Get High Performance From C, No Assembly Required

Designers are asking their DSP cores to do more and more of the heavy workloads required for highly complex algorithms for filtering, FFT, MIMO, and other signal processing intensive applications. To get high performance from a conventional DSP core, developers have traditionally used assembly code programming, which is time consuming and difficult to debug.

Advances in state-of-the-art DSP architectures and companion compilers now make it possible for developers to keep their algorithms in C and still get the performance they need from a general-purpose high-performance DSP.

The magic is in the compiler technology. This white paper explains how Tensilica's ConnX D2 DSP engine coupled with the advanced Tensilica XCC compiler can help you get equivalent or better performance using standard C than other DSPs programmed in assembly code. The result: you can get your project finished much faster.

Tensilica Hat Spotted at Wimbledon!

Here's Mrs. Tim Penhale-Jones wearing her Tensilica hat at the ladies final day, centre court Winbledon. Where do you wear your Tensilica hat? Email me a picture and I'll be proud to post it. She's the wife of our European sales director and I'm sure she has a first name but I don't know it. Do you need a hat to take on your next adventure? Send me an email.

New Job Posting: Staff Logic Design Engineer in Santa Clara

We're hiring lots of engineers (and one corporate attorney) in Santa Clara, Pune, and Beijing. Keep checking our Careers page for the latest updates. We're growing!

Newest SOC Design Partner: Dream Chip Technologies (DCT)

Welcome DCT - our newest design center in Garbsen, Germany. They have extensive Tensilica expertise, particularly in low-power multimedia designs. They really know their TIE, and can help our customers get the lowest possible power and most efficiency with their customizable processor designs.

White Paper: Using Processors in the SOC Dataplane

To effectively use processors in the dataplane, designers need a quick, fool-proof way to customize those processors for the exact task at hand. A dataplane processor (or "DPU") naturally connects to existing RTL blocks and provides additional computational horsepower tailored to the exact data type needed - all this with less effort than hand-coding RTL finite state machines or microcoded engines.This is a great white paper to help you understand how you can apply processors for dedicated functions in the dataplane.

Looking for the Best PC Graphics?

Tensilica's processors configured to accelerate video stream decoding are an ingredient in every UVD-powered AMD ATI graphics chip, including those with ATI Avivo HD video and display technology, which provdes PC users with crisp images, smooth videos and true-to-life colors. UVD is a dedicated video decode processing unit that offloads the CPU from the decoding process. UVD technology reduces power use, helps decrease system noise and helps to increase notebook battery life during HD video playback. AMD's graphics products provide for DirectX10 and DirectX11 gaming and allow PCs to be hooked up to big-screen TVs with HDMI and built-in 5.1 surround sound audio to enjoy Blu-ray and HD DVD movies.

UVD-powered AMD ATI graphics chips include the HD5000 serires, HD4000 series, the HD3000 series, the HD2000 series, the x1900 series, the x1600 series, and the x1300 series.  See some of them at our web site.

Good Summer Reading: Using Processors in the SOC Dataplane

To effectively use processors in the dataplane, designers need a quick, fool-proof way to customize those processors for the exact task at hand. A dataplane processor (or "DPU") naturally connects to existing RTL blocks and provides additional computational horsepower tailored to the exact data type needed - all this with less effort than hand-coding RTL finite state machines or microcoded engines. With a DPU's programmability, designers now have the flexibility to make changes close to and after silicon production. This white paper explains how DPUs can be effectively used in the SOC dataplane.