Wednesday, May 11, 2005
Tensilica and EVE Speed SoC Development Times
Tensilica is working with Emulation and Verification Engineering (EVE) to speed the design of complex SoCs with multiple Xtensa processors. Tensilica’s customers will be able to download pre-verified RTL code produced by Tensilica’s Xtensa Processor Generator into EVE’s hardware prototyping platform for integrated whole-chip design verification. Tensilica’s Xtensa Xplorer development environment will be linked to EVE’s ZeBu hardware-based verification product to provide hardware/software co-verification and improve overall SoC simulation and debugging. By providing our users with easy access to EVE’s ZeBu prototyping platform, they should be able to quickly verify their entire SOC designs.
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3 comments:
Do you have an Rss feed to subscribe to. If can ever get my aggregator to work I'll be set. It may be because I'm spending so much time reading about ##KEYWORD## . It's been an obsession for the last year now. Sorry, I'm thinking aloud and probably boring you with prototyping thoughts.
Is this blog feed live? I'd like to subscribe to it using my aggregator. It's possible that my site rapid prototyping can get your feed automatically so I can keep up with our design and cnc posts here.
Is this blog feed live? I'd like to subscribe to it using my aggregator. It's possible that my site rapid prototyping can get your feed automatically so I can keep up with our design and cnc posts here.
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