By embedding functionality right into the processor datapath itself, designers can use the Xtensa 8 DPU to not only perform control functions, but also some of the finite state machine tasks that manage RTL blocks and some of the RTL functionality as well. This makes for a smaller, more efficient chip design, and it significantly reduces the verification challenges associated with new RTL designs. See http://www.tensilica.com/products/xtensa-customizable/xtensa.htm
All the news you're looking for from Tensilica, Inc. Find out how you can use Tensilica's customizable, extensible processors to speed your SOC design. See Tensilica for DSPs and all the processing you need to do in the dataplane (dataplane processors - DPUs).